STRUCT DRM_DP_MST_TO(9)

NAME
struct_drm_dp_mst_topology_mgr - DisplayPort MST manager

SYNOPSIS

struct drm_dp_mst_topology_mgr {
  struct device * dev;
  struct drm_dp_mst_topology_cbs * cbs;
  struct drm_dp_aux * aux;
  int max_payloads;
  int conn_base_id;
  struct drm_dp_sideband_msg_rx down_rep_recv;
  struct drm_dp_sideband_msg_rx up_req_recv;
  struct mutex lock;
  bool mst_state;
  struct drm_dp_mst_branch * mst_primary;
  bool guid_valid;
  u8 guid[16];
  u8 dpcd[DP_RECEIVER_CAP_SIZE];
  int pbn_div;
};

MEMBERS

dev
    device pointer for adding i2c devices etc.

cbs
    callbacks for connector addition and destruction. max_dpcd_transaction_bytes - maximum number of bytes to read/write in one go.

aux
    aux channel for the DP connector.

max_payloads
    maximum number of payloads the GPU can generate.

conn_base_id
    DRM connector ID this mgr is connected to.

down_rep_recv
    msg receiver state for down replies.

up_req_recv
    msg receiver state for up requests.

lock
    protects mst state, primary, guid, dpcd.

mst_state
    if this manager is enabled for an MST capable port.

mst_primary
    pointer to the primary branch device.

guid_valid
    GUID valid for the primary branch device.

guid[16]
    GUID for primary port.

dpcd[DP_RECEIVER_CAP_SIZE]
    cache of DPCD for primary port.

pbn_div
    PBN to slots divisor.

DESCRIPTION

This struct represents the toplevel displayport MST topology manager. There should be one instance of this for every MST capable DP connector on the GPU.

AUTHORS

Jesse Barnes <jesse.barnes@intel.com>
Intel Corporation,

    Initial version

Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Ideas on board SPRL,

    Driver internals

Daniel Vetter <daniel.vetter@ffwll.ch>
Intel Corporation,

    Contributions all over the place

COPYRIGHT